Chinese Chipmakers Squeeze More from Older Machines at a Higher Price

China's semiconductor industry is successfully bypassing the lack of extreme ultraviolet lithography equipment by using older deep ultraviolet machines, but the workaround is driving up production costs and increasing the risk of defects. Export controls have kept ASML's advanced EUV tools out of the country, forcing local chipmakers to rely on DUV technology. By exposing critical chip layers multiple times, these factories can still produce capable silicon, yet the process is slower and more expensive than the single-pass method used by Western competitors.

The numbers highlight the financial and physical trade-offs involved in this approach. Industry experts note that three exposures on a 193 immersion tool cost roughly the same as one EUV pass. However, when manufacturers require four masks, EUV becomes the cheaper option. Each additional exposure introduces the potential for alignment errors, which can reduce the number of usable chips per wafer. Since wafers cost tens of thousands of dollars, losing usable space is a significant financial burden for manufacturers.

Despite these hurdles, China has made notable progress. A 2023 teardown of the Huawei Mate 60 Pro revealed that its Kirin 9000S processor was manufactured by SMIC using a second-generation 7nm-class process without EUV. More recent analysis suggests SMIC has moved its DUV-based process closer to the density associated with 5nm manufacturing. While this still trails the leading processes from TSMC and Samsung, it demonstrates that the technology can be stretched further than previously expected.

The memory sector provides further evidence of this efficiency gap. Morgan Stanley estimates that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western rivals. The bank described lithography access as a hard ceiling for Chinese memory development. Chris Mack, co-founder and CTO of Fractilia, emphasized that node labels like 5nm or 3nm have little meaning without considering the underlying process economics. He noted that SMIC's progress, while real, remains significantly less scaled than established 5nm processes from major competitors.

There is still room to improve with DUV technology. Micron developed its 1-alpha DRAM without EUV by using tight process control and multiple patterning. Mack stated that Micron pushed the 193 technology farther than other memory makers. Morgan Stanley believes CXMT's planned move to 1-alpha DRAM for HBM3e is achievable without EUV. Douglas Fuller, a researcher at Copenhagen Business School, expects advanced packaging will allow firms to use DUV for the latest DRAM generations by the end of the decade.

Even so, the limitations are clear. Micron eventually turned to EUV for its 1-gamma DRAM, which offers more than 30% greater bit density than the previous generation. Mack said he would be hard pressed to believe a 3nm or 2nm node could be economically viable without EUV. However, Chinese chipmakers are not expected to stop. They can continue pushing DUV while accepting larger dies and poorer yields, or they can add capacity. Morgan Stanley projects CXMT's share of global DRAM bit supply will rise from 14% in 2026 to 16% in 2028 through new capacity.

The long-term outlook remains mixed. China's AI chip self-sufficiency is expected to rise from 42% in 2025 to 70% by 2030. Yet, persistent gaps in EUV access, high-bandwidth memory, and advanced software will likely remain. The industry is adapting, but the cost of that adaptation is becoming increasingly visible in both production times and final chip performance.